CMOS voltage multiplier

Details CMOS voltage multiplier CMOS voltage multiplier

1989-06-28

1990-05-01

Wong, Peter S.

Electric power conversion systems

Current conversion

With voltage multiplication means

307246, 307110, H02M 719

Patent

active

049224026

ABSTRACT:
A wholly integrated, multistage, CMOS voltage multiplier utilizes as a diode structure for transferring electric charge from an input node to an output node of each stage an enhancement type MOS transistor, the gate of which is coupled to the same switching phase to which the output capacitor of the stage is connected by means of a coupling capacitor. During a semicycle of charge transfer through said MOS transistor, the coupling capacitor charges through a second MOS transistor of the same type and having the same threshold of said charge transfer MOS transistor, connected in a diode configuration between the output node of the stage and the gate of the charge transfer MOS transistor, in order to cut-off the latter when reaching a voltage lower than the voltage reached by the output node by a value equal to the threshold value of said second transistor. In this way, a significant voltage drop across the charge transfer transistor is efficiently eliminated, thus allowing the generation of a sufficiently high output voltage though having available a relatively low supply voltage.

REFERENCES:
patent: 3790812 (1974-02-01), Fry
patent: 4061929 (1977-12-01), Asano
patent: 4344003 (1982-08-01), Harmon et al.
patent: 4398099 (1983-08-01), Benoit-Gonin et al.
patent: 4621315 (1986-11-01), Vaughn et al.
patent: 4839787 (1989-06-01), Kojima et al.

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