CMOS voltage level translator circuit

Details CMOS voltage level translator circuit CMOS voltage level translator circuit

1991-08-07

1992-08-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307291, 307451, 307264, 307585, H03K 190175, H03K 329, H03K 19094, H03L 500

Patent

active

051361906

ABSTRACT:
An improved CMOS voltage level translator circuit having an interface stage, an intermediate stage and an output stage is presented. The inventive circuit is characterized by low crossover current in the output and intermediate stages while maintaining minimal delay response when translating a lower potential signal into a higher potential signal. The improved translator circuit may be used in applications such as during EEPROM programming where control signals with normal voltage TTL voltage swing of V.sub.CC and V.sub.SS need to interface with the EEPROM row decoders which require a much higher voltage swing of V.sub.CC ' (>V hd CC) and V.sub.SS.

REFERENCES:
patent: 4958091 (1990-09-01), Roberts
patent: 4978870 (1990-12-01), Chen et al.
patent: 4996443 (1991-02-01), Tateno
"An Experimental 4-Mb Flash EEPROM with Sector Erase" IEEE Journal of Solid State Circuits, vol. 26, No. 4, Apr. 1991, pp. 484-491.

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