CMOS type solid imaging device

Details CMOS type solid imaging device CMOS type solid imaging device

1999-04-22

2002-09-10

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making device or circuit responsive to nonelectrical signal

Responsive to electromagnetic radiation

C438S075000, C438S298000, C438S312000, C257S292000

Reexamination Certificate

active

06448104

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field Of The Invention
The present invention relates to a solid imaging device which provides high sensitivity.
2. Description Of The Related Art
CMOS type image sensors, i.e., image sensors formed through a CMOS process, have been proposed. CMOS type image sensors are classified into: PPS (passive pixel sensors) for reading a signal charge which has been generated through photoelectric conversion in each pixel without alteration to the signal charge; and APS (active pixel sensors) for reading such a signal charge after having been amplified, the amplification occurring on a pixel-to-pixel basis. Both types of CMOS image sensors usually employ a photodiode (constituting a p-n junction) as a photoelectric conversion section.
In a PPS type CMOS image sensor, as shown in
FIG. 9
, a signal charge from a photodiode
5
is switched via a single MOS transistor
3
, which is located within the same pixel, so as to be read onto a signal line
13
without being amplified. A signal for causing the switching of the MOS transistor
3
is supplied via a pixel selection clock line
11
.
FIG. 10A
shows a plan view of an actual pattern corresponding to the circuit diagram shown in FIG.
9
.
FIG. 10B
shows a cross-sectional view taken along line A—A of FIG.
10
A.
FIG. 10C
shows a cross-sectional view taken along line B—B of FIG.
10
A. In
FIG. 10A
, the elements which correspond to any circuit elements shown in
FIG. 9
(e.g., the photodiode
5
) are indicated by the same reference numerals as used therein.
As seen from
FIGS. 10B and 10C
, the photodiode
5
for performing photoelectric conversion is constructed from an n
+
layer
130
formed on a p well
110
, which in turn is formed on a p
−
semiconductor substrate
100
. A p-n junction is formed at an interface between the n
+
layer
130
and the p well
110
, where photoelectric conversion takes place. The n
+
layer
130
is divided into a portion
130
a
(the hatched portion in
FIG. 10A
) which substantially functions as a photosensitive portion (i.e., a photodiode) and a portion
130
b
which substantially functions as a source/drain of the MOS transistor
3
. These portions
130
a
and
130
b
are usually formed in an integral manner. In the step of forming the n
+
layer
130
composing the photodiode
5
, an n
+
layer
131
(which later becomes the source/drain of the MOS transistor
3
) is formed, usually concurrently, on the p well
110
so as to be located-at a predetermined distance from the n
+
layer
130
. As a result, a channel
3
a
of the MOS transistor
3
is formed in the p well
110
. By disposing the pixel selection clock line
11
above the channel
3
a
with an insulation layer (e.g., an oxidation film; not shown) interposed therebetween, and applying a predetermined voltage thereto, a switching operation of the MOS transistor
3
occurs. Thus, the MOS transistor
3
is activated or turned on so that a signal (charge) from the photodiode
5
is transmitted, via a contact formed in the source/drain n
+
layer
131
, to a signal line
13
(not shown in
FIG. 10A
) which is formed so as to intersect the clock line
11
.
On the other hand, an APS type CMOS image sensor requires a photoelectric conversion section, an amplification section, a pixel selection section, and a reset section to be formed in association with each pixel. Usually, three to four MOS transistors (T) are employed in addition to a photodiode (PD).
FIG. 11
shows an exemplary structure of a portion of an APS type CMOS image sensor corresponding to two pixels, where three transistors (T) and one photodiode (PD) are incorporated (Mabuchi et al., “A ¼ INCH 330K PIXEL VGA CMOS IMAGE SENSOR”, a technical report of the Institute of Image Information and Television Engineers, IPU97-13, March 1997”). As shown in
FIG. 11
, a photodiode
5
, an amplification section
1
. a reset section
2
, a pixel selection section
3
; a pixel selection clock line
11
, a reset clock line
12
, a signal line
13
, and a supply line
14
are provided for each pixel.
FIG. 12A
shows a plan view of an actual pattern corresponding to the circuit diagram shown in FIG.
11
.
FIG. 12B
shows across-sectional view taken along line A—A of FIG.
12
A.
FIG. 12C
shows a cross-sectional view taken along line B—B of FIG.
12
A. In
FIG. 12A
, the elements which correspond to any circuit elements shown in
FIG. 11
(e.g., the photodiode
5
) are indicated by the same reference numerals as used therein. The photodiode
5
and three transistors
1
to
3
are formed so as to be aligned along the vertical direction in FIG.
12
A.
As seen from
FIGS. 12B and 12C
, the photodiode
5
for performing photoelectric conversion is constructed from an n
+
layer
130
formed on a p well
110
, which in turn is formed on a p
−
semiconductor substrate
100
. A p-n junction is formed at an interface between the n
+
layer
130
and the p well
110
, where photoelectric conversion takes place. In the step of forming the n
+
layer
130
composing the photodiode
5
, n
+
layers
131
(which later become the respective source/drains of the MOS transistors
1
to
3
) are formed, usually concurrently, on the p well
110
so as to be positioned at predetermined distances from the n
+
layer
130
.
In
FIGS. 9
to
12
A,
12
B, and
12
C, the transistors
1
,
2
, and
3
are all n type MOS transistors, and the photodiode
5
is a p-n junction type diode. Such elements can be easily formed by using a standard CMOS process.
Now, the operation principles of a photodiode will be briefly discussed with reference to
FIGS. 13A and 13B
. Light which enters a p-n junction of a photodiode will be subjected to photoelectric conversion before it reaches an ingression depth Lp (on average), thereby generating electron/hole pairs.
FIG. 13B
shows the light intensity of the incident light against the depth as taken from the substrate surface. The amount of electrons which are effectively stored in the n surface layer as a signal charge is defined as a sum of the following three components:
(i) all of the electrons that have been generated in a depletion layer which is formed at the p-n junction interface;
(ii) a number of electrons equivalent to the number of the holes generated in a neutral region of the n layer that have reached, through diffusion, the end of the depletion layer formed at the junction interface; and
(iii) a number of electrons generated in a neutral region of the p layer that have reached, through diffusion, the end of the depletion layer formed at the junction interface.
Therefore, enhancement of sensitivity can be most efficiently achieved by expanding the area of the depletion layer (component (i)). Component (ii) increases as the diffusion length of the holes within the n layer becomes larger than the n layer junction depth Xj (FIG.
13
A). Component (iii) increases as the diffusion length of the electrons within the p layer increases. However, an increase in the diffusion length of the electrons in the p layer results in more eminent crosstalk occurring between adjoining pixels, resulting in problems such as decrease in the resolution and/or a flare phenomenon (i.e., influence of irradiation of intense light on other regions).
In the structures illustrated in
FIGS. 9
;
10
A to
10
C;
11
; and
12
A to
12
C, the photodiode
5
is formed on the CMOS-process-based p well
110
. In particular, in the APS type CMOS image sensor shown in
FIGS. 11 and 12A
to
12
C, the area occupied by the transistors
1
to
3
must be minimized in order to secure a large photodiode area. Reducing the transistor dimensions requires increasing the p type impurity concentration in the p well
110
. However, as shown in
FIG. 13A
, an increased p type impurity concentration in the p well
110
results in a decrease in the thickness Xdep of the depletion layer formed at the p-n junction interface.
In the following discussion, silicon is exemplified as a semiconductor substrate material.
In a

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