CMOS twin-tub negative voltage switching architecture

Details CMOS twin-tub negative voltage switching architecture CMOS twin-tub negative voltage switching architecture

1997-08-27

1999-11-30

Wells, Kenneth B.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

327540, 327415, G05F 110

Patent

active

059949481

ABSTRACT:
A CMOS twin-tub negative voltage switching architecture is for a non-volatile memory device and includes a negative voltage multiplier for generating a increased voltage value starting from a single main power supply. A voltage regulator feedback is connected to the voltage multiplier for regulating the generated negative voltage value; and a plurality of independent switch circuits each one receiving as an input the negative voltage value and producing as an output a predetermined local negative voltage.

REFERENCES:
patent: 5029282 (1991-07-01), Ito
patent: 5043858 (1991-08-01), Watanabe
patent: 5093586 (1992-03-01), Asari
patent: 5140182 (1992-08-01), Ichimura
patent: 5335200 (1994-08-01), Coffman et al.
patent: 5668494 (1997-09-01), Nicollini et al.
patent: 5754476 (1998-05-01), Caser et al.

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