CMOS twin cell non-volatile random access memory

Static information storage and retrieval – Floating gate – Particular connection

Reexamination Certificate

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Details

C365S185050, C365S185140, C365S185190, C365S202000

Reexamination Certificate

active

07746696

ABSTRACT:
A memory has first and second storage cells, each with a floating node, that store complementary data values. Interlaced inverters quickly sense a voltage difference between the storage cells and provide a data value output when the memory is read. Each floating node includes a tunneling gate of a tunneling transistor, a gate of a bitline transistor, and a plate of a coupling capacitor.

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patent: 2007/0247914 (2007-10-01), Fang et al.

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