CMOS TTL input buffer using a ratioed inverter with a threshold

Details CMOS TTL input buffer using a ratioed inverter with a threshold CMOS TTL input buffer using a ratioed inverter with a threshold

1989-10-27

1991-05-21

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307464, H03K 1994, H03K 1992, H03K 1903, H03K 1714

Patent

active

050178113

ABSTRACT:
The invention applies a weak forward bias to the body of the NFET transistor of a PFET-NFET TTL inverter buffer circuit to lower the NFET threshold voltage by about 0.45 volts, as a result of 1.5.mu. amps of body-source current providing a body to source voltage of about 0.5 volts to achieve a near ideal switch point of 1.45 volts under nominal conditions. Also a modified inverter circuit with biasing source, two diodes for trip voltage of 1.4 volts and a comparator constitute a central bias generator for supplying proper bias to the body of the NFETs of a plurality of TTL input buffers.

REFERENCES:
patent: 4471242 (1984-09-01), Noufer et al.
patent: 4593212 (1986-06-01), Svager
patent: 4612461 (1986-09-01), Sood

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