CMOS tri-mode input buffer

Details CMOS tri-mode input buffer CMOS tri-mode input buffer

1991-08-12

1992-06-23

Pascal, Robert J.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

H03K 1900

Patent

active

051245906

ABSTRACT:
A CMOS tri-mode input buffer for generating three groups of binary codes at first and second output nodes in response to an input signal having three different voltage levels includes an output stage (20), first output buffer (22), a second output buffer (24), a first inptu circuit (26), and a second input circuit (28). The output stage (20) generates first and second output signals (Q1, Q2) at the respective first and second output noes (16, 18). The first output buffer is responsive to the first output signal (Q1) for generating a first buffered input signal (U1) which is CMOS logic compatible. The second output buffer (24) is responsive to the second output signal (Q2) for generating second buffered output signal (U2) which is CMOS logic compatible.

REFERENCES:
patent: 4287433 (1981-09-01), Goodspeed
patent: 4864166 (1989-09-01), Gloaguen
patent: 4967102 (1990-10-01), Mahler
patent: 5045728 (1991-09-01), Crafts

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