CMOS tree decoder with speed enhancement by adjustment of gate w

Details CMOS tree decoder with speed enhancement by adjustment of gate w CMOS tree decoder with speed enhancement by adjustment of gate w

1984-07-10

1987-08-04

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307463, H03K 19017, H03K 19094

Patent

active

046848290

ABSTRACT:
A semi-conductor decoder circuit includes 2.sup.N-1 circuits each formed of transistors vertically arranged in N stages, with the transistors of 2.sup.N-1, 2.sup.N-2 . . . 2.sup.1, 2.sup.0 number being disposed sequentially from the output stage in N stages in a tree structure. The gate width of the transistor at each stage is expanded as a distance from the output stage is increased so as to prevent an increase in ON resistance of the circuit and also to achieve a high speed operation.

REFERENCES:
patent: 3355598 (1967-11-01), Tuska
patent: 3539823 (1970-11-01), Zuk
patent: 4140924 (1979-02-01), Oguey et al.
patent: 4176287 (1979-11-01), Remedi
patent: 4430583 (1984-02-01), Shoji
patent: 4491839 (1985-01-01), Adam
Kenyon et al, "Complementary Field-Effect Transistor High-Density Decoder", IBM-TDB; vol. 15, No. 9, pp. 2823-2824, 2/1973.
Gersbach et al, "Cascode Decoder"; IBM-TDB, vol. 8, No. 4, pp. 642-643; 9/1965.
Herzog; "COS/MOS: the Best of Both Worlds"; Electronics; 2/17/1969; pp. 109-112.

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