CMOS Transistor pair with reverse biased substrate to prevent la

Details CMOS Transistor pair with reverse biased substrate to prevent la CMOS Transistor pair with reverse biased substrate to prevent la

1979-09-19

1982-04-27

Clawson, Jr., Joseph E.

357 43, 357 86, H01L 2702

Patent

active

043273688

ABSTRACT:
A complementary type MOS transistor device is disclosed including a p-channel type MOS transistor having source, drain and gate regions formed in the n-well region which is formed in the surface area of a p-type semiconductor layer and an n-channel MOS transistor having source, drain and gate regions formed in said semiconductor layer. The semiconductor layer is formed on an n-type semiconductor body and a reverse bias voltage is applied between the semiconductor layer and the semiconductor substrate.

REFERENCES:
patent: 4032952 (1977-06-01), Ohba et al.
patent: 4063274 (1977-12-01), Dingwall
patent: 4112670 (1978-09-01), Morozumi

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