Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1988-04-11
1989-09-12
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307443, 307451, 307543, 307546, H03K 1716, H03K 19094, H03K 19017
Patent
active
048663085
ABSTRACT:
A high speed, high performance CMOS to GPI interface circuit is disclosed. The interface circuit contains an input stage, clamping circuitry, an output stage and feedback circuitry. The clamping circuitry clamps the voltage level presented to the output stage at a level below the power supply voltage when the input from the CMOS circuit is at a high logic level. As the voltage level of the signal presented to the CPI circuitry rises, feedback circuitry feeds this signal back to the clamping circuitry, which in turn decreases the voltage level presented to the output stage. This assures the signal presented to the GPI circuit falls within the specified voltage level from 1.51 and 2.2 volts. The feedback circuitry contains a single pole filter that filters out high frequency reflections presented to the feedback circuitry, and a slew rate limiter that slows the rise and fall of the voltage level presented to the output stage thereby reducing noise on the power supply and ground lines. The feedback circuitry uses bilateral (push-pull) gain techniques to control the voltage level presented to the output stage as the input signal from the CMOS circuit swings from low to high logic levels. The interface circuit is made up exclusively from standard threshold FETs. The interface circuit also contains discharge circuitry that discharges the voltage level of the feedback circuitry when the input from the CMOS circuit changes from a high level to a low level, thereby preventing a latch-up condition.
REFERENCES:
patent: 4255670 (1981-03-01), Griffith
patent: 4454432 (1984-06-01), Wood
patent: 4472647 (1984-09-01), Algood et al.
patent: 4477741 (1984-10-01), Moser, Jr.
patent: 4527078 (1985-07-01), Smith
patent: 4538076 (1985-08-01), Shimada
patent: 4563601 (1986-01-01), Asano et al.
patent: 4593212 (1986-06-01), Svager
patent: 4704549 (1987-11-01), Sanwo et al.
patent: 4760292 (1988-07-01), Bach
IBM Tech. Disc. Bul., vol. 30, No. 2, Jul. 1987, "CMOS Driver Circuit".
IBM Tech., Disc. Bul., vol. 29, No. 4, Sep. 1986, "CMOS Driver with Output Level Control".
IBM Technical Disclosure Bulletin, vol. 30, No. 2, Jul. 1987, pp. 770-771.
IBM Technical Disclosure Bulletin, vol. 29, No. 4, Sep. 1986, pp. 1760-1761.
IBM Technical Disclosure Bulletin, vol. 30, No. 6, Nov. 1987, pp. 66-67.
IBM Technical Disclosure Bulletin, vol. 29, No. 11, Apr. 1987, pp. 4929-4930.
IBM Technical Disclosure Bulletin, vol. 29, No. 4, Sept. 1986, p. 1697.
IBM Technical Disclosure Bulletin, vol. 29, No. 1, Jun. 1986, pp. 296-297.
Cecchi Delbert R.
Kim Hyung S.
Mitby John S.
Stanisic Balsha R.
Swart David P.
International Business Machines - Corporation
Miller Stanley D.
Rose Curtis G.
Wambach M.
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