CMOS to ECL translator circuit and methodology

Details CMOS to ECL translator circuit and methodology CMOS to ECL translator circuit and methodology

1990-06-29

1992-03-31

Nelms, David C.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307455, 307482, 307264, H03K 19092, H03K 19094, H03K 1902, H03K 19086

Patent

active

051011239

ABSTRACT:
A translator circuit 82 and operation thereof is disclosed including a control signal generator 48 and an ECL output buffer circuit 84. Control signal generator 48 includes a CMOS inverter comprising transistors 52 and 54. The CMOS inverter is connected to a bipolar junction transistor (BJT) 70 which is further connected to as BJT 76. BJT 70 provides a voltage control signal, V.sub.CS, to ECL output buffer circuit 84. BJT 76 is connected as a transistor in a differential pair comprising transistors 76 and 86. An ECL output signal, V.sub.OUT, is generated in accordance with the operational state of transistors 76 and 86 and additional circuitry associated therewith.

REFERENCES:
patent: 4656375 (1987-04-01), Lauffer et al.
patent: 4835420 (1989-05-01), Rosky
patent: 4849659 (1989-07-01), West
patent: 4912347 (1990-03-01), Morris
patent: 4926065 (1990-05-01), Coy et al.
patent: 4945265 (1990-07-01), Estrada
BiCMOS Technology and Applications edited by A. R. Alvarez, published by Kluwer Academic Publishers, 1989.

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