CMOS to ECL output buffer circuit

Details CMOS to ECL output buffer circuit CMOS to ECL output buffer circuit

1989-02-13

1990-08-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 307356, 307358, H03K 19092, H03K 19086, H03K 19003, H03K 1710

Patent

active

049470612

ABSTRACT:
Disclosed is an output buffer circuit which converts from CMOS to ECL voltage levels using only CMOS technology. An external resistor provides the buffer with reference voltage levels in combination with a reference circuit. The high and low voltage references are coupled to the gates of separate biasing transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output. In the first case, the low voltage level is established, and in the second case, the high voltage level is set. Additional transistors can be provided to remove charge buildup on the third transistor.

REFERENCES:
patent: 4792704 (1988-12-01), Lobb et al.
patent: 4794282 (1988-12-01), Colles
patent: 4797583 (1989-01-01), Ueno et al.
patent: 4800303 (1989-01-01), Graham et al.
patent: 4806799 (1989-02-01), Pelley, III et al.
Fairchild F100K ECL Data Book, pp. 3-38 to 3-40 (1986).
IEEE International Solid State Circuits Conference Digest of Technical Papers, "A 2 .mu.m CMOS Digital Adaptive Equalizer Chip for QAM Digital Radio Modems," by S. Meier, E. DeMan, T. G. Noll, U. Loibl, and H. Klar, pp. 64-65 and 302-303 (1988).
IEEE Journal of Solid State Circuits, "A 140 Mbit/s CMOS LSI framer Chip for a Broad-Band ISDN Local Access System," by H. J. Chao, T. J. Robe, and L. S. Smoot, pp. 133-141 (1988).
Unpublished, "A CMOS VLSI Framer Chip for a Broadband ISDN Local Access System", by H. J. Chao, T. J. Robe, and L. S. Smoot, pp. 1-15 and FIGS. 1-13.

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