CMOS to ECL level translator

Details CMOS to ECL level translator CMOS to ECL level translator

1991-12-17

1994-05-10

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307455, H03K 19092, H03K 19094

Patent

active

053110820

ABSTRACT:
A low power CMOS to ECL level translator especially suitable for use as an output level translator includes a CMOS switch having a P-channel MOSFET transistor and an N-channel MOSFET transistor connected to CMOS voltage levels V.sub.DD and V.sub.SS, an NPN bipolar transistor having a base connected to the output of the CMOS switch through an equalization circuit, a collector connected to ECL potential V.sub.CC, and an emitter connected to an ECL potential V.sub.EE. The ECL output is taken directly from the emitter of the bipolar transistor. The equalization circuit includes a PMOS transistor (or parallel transistor array if a greater size is needed) connected between V.sub.CC and the base of the bipolar transistor, the gate or gates thereof being connected to the output of the CMOS switch; and a second PMOS transistor connected between the base and emitter of the bipolar transistor, the gate thereof being connected to the DATA terminal. When the CMOS level is a logic zero, the equalization circuit isolates the base of the bipolar transistor from V.sub.CC, and shorts the base and emitter of the bipolar transistor, effectively tristating the level translator while avoiding reverse-biasing the bipolar transistor. When the CMOS level is a logic one, the equalization circuit isolates the base from the emitter and raises the base toward V.sub.CC, thereby driving the ECL output terminal. An enable circuit for the level translator also is described. The level transistor is suitable for use as an output translator, as an element of a bidirectional output translator, and when combined with a clamping circuit, as an internal level translator.

REFERENCES:
patent: 4656372 (1987-04-01), Sani et al.
patent: 4704549 (1987-11-01), Sanwo et al.
patent: 4890019 (1989-12-01), Hoyte et al.
patent: 5036224 (1991-07-01), Wendell
patent: 5047671 (1991-09-01), Suthar et al.
patent: 5101123 (1992-03-01), Ten Eyck
IEEE JSSC, vol. 25 No. 1, Feb. 1990, "High-Performance BiCMOS 100k-Gate Array", by Gallia et al.
"BiCMOS Technology and Applications" by Alvarez, 1989, `6.4.2 CMOS to ECL`.

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