CMOS to ECL converter-buffer

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307445, 307448, 307451, 307264, 307571, 307576, H03K 19092, H03K 1920, H03K 19017, H03L 500

Patent

active

047045493

ABSTRACT:
The circuit of the present invention converts CMOS logic level signals to corresponding ECL logic level signals to permit the coupling of CMOS and ECL devices. In addition, the present invention maintains a relatively constant impedance as the logic levels on its output change. The circuit has an input terminal connectable to a source of a first set of logic signals and an output terminal connectable to a device that is responsive to a second set of logic level signals. First and second power terminals are provided for connection to first and second power supplies, respectively. A transistor of first conductivity type having first, second and gate terminals is provided with the gate terminal connected to the input terminal and the first terminal connected to the first power supply terminal. A second transistor of opposite conductivity type having a first, second and gate terminal is provided with the gate terminal of the second transistor connected to the second terminal of the first transistor. The second terminal of the second transistor is connected to the output terminal and the first terminal of the second transistor is connected to the second power supply terminal. A saturation means is connected between the gate terminal and the second terminal of the second transistor. The saturation means is responsive to the signal on the input terminal for saturating the second transistor in an "ON" state when the logic level 0 is applied to the input terminal.

REFERENCES:
patent: 4563601 (1980-01-01), Asano et al.

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