CMOS technology voltage booster

Details CMOS technology voltage booster CMOS technology voltage booster

2000-12-15

2002-07-16

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

With specific source of supply or bias voltage

C327S537000

Reexamination Certificate

active

06420926

ABSTRACT:

TECHNICAL FIELD
This invention relates to a CMOS technology voltage booster, and more particularly but not exclusively, to a novel voltage booster comprising NMOS transistors and being adapted for operation on specially low voltages in the range of 1V.
Specifically, the disclosed embodiment of the invention relates to a voltage booster as above that includes a plurality of charge-pump stages cascade-connected together and driven by a plurality of phases, each stage having a terminating input node and a terminating output node with at least one transistor connected therebetween which has its control terminal connected to an internal circuit node of the same stage and applied to one of the phases.
BACKGROUND OF THE INVENTION
Voltage boosters are extensively utilized in non-volatile memory devices, such as EEPROMs and Flash EEPROMs, to generate a voltage Vp needed for the device program phase. These voltage boosters include circuit portions of a kind known as charge pumps.
The circuit architectures more frequently employed to provide voltage boosters for memories are based essentially on a Dickson charge pump, shown diagrammatically in FIG.
1
.
The principle of operating such a charge pump will be briefly reviewed herein below, which assumes an initial state of the control signal CLK
1
to be 0 and the signal CLK
2
, in phase opposition with the former, to be a voltage value Vck, as shown in FIG.
1
A.
In these conditions, the capacitor C(
1
) is in a charged state at a voltage Vcc−Vth(D
1
). When CLK
1
has a leading edge at Vck, the node
1
will attain a voltage Vcc+Vck−Vth(D
1
), since the voltage across the capacitor cannot change instantaneously. Thus, the diode D(
2
) begins to conduct and the capacitor C(
1
) transfers charge into the capacitor C(
2
).
When the signal CLK
1
goes back to 0 and the other signal CLK
2
rises to Vck, the diode D(
1
) is reverse biased and prevents the charge transferred into C(
2
) from flowing back, while the diode D(
2
) allows the charge to pass from the capacitor C(
2
) to the capacitor C(
3
). This process is iterated at all the stages.
In CMOS circuits, the diode is usually in the form of an N-channel transistor having a low threshold voltage and being diode-connected.
Shown diagrammatically in
FIG. 2
are two contiguous stages of a conventional CMOS technology voltage booster.
With the charge pump delivering current, the output voltage is given generally as:
Vout=Vcc−Vth(
1
)+&Sgr;[Vck′−Vth(i)−Iout/f(C+CP)]
where:
Cp is the parasitic capacitance of a node;
Vth(i) is the body-effect threshold voltage of the ith transistor;
Vck′corresponds to Vck*C/(C+Cp);
lout is the current supplied by the charge pump to the load; and
f is the clock frequency.
A major limitation comes to a pump of this type from the threshold loss that is incurred at each stage. This limitation is emphasized by the body effect of the transistor. To overcome the threshold loss problem, the prior art provides a four-phase circuit architecture, shown in FIG.
3
.
The operation of the circuit of
FIG. 3
will be explained with the aid of a phase plot, shown schematically in FIG.
3
A.
Assume an initial state of the voltage V
1
at the node
1
to be the same as the voltage V
2
at the node
2
. The first phase Fx is brought to a high value, raising the voltage V
1
at the node
1
by a value Fx′ equal to Fx*Cc/(Cc+Cpar).
The nodes
2
and
3
are unchanged because the transistors M
1
and M
2
are in their ‘off’ state. The second phase Fbx goes high, somewhat delayed on the first phase Fx, thereby raising the voltage V
2
at the node
2
by a value Fbx′ equal to Fbx*Cb/(Cb+Cpar′).
If this voltage Fbx′ is higher than the threshold voltage of the transistor M
2
, the charge stored in the capacitor Cc(i) can be transferred into the capacitor Cc(i+1). Therefore, the second phase Fbx goes back to zero causing the transistor M
1
to be turned off, so that no charge backflow will occur as the first phase Fx also goes back to zero after a delay.
At this point, the process is iterated at the following stages.
It should be noted that when the third phase Fn goes high, the transistor M
2
is turned on to short the nodes
1
and
2
. In this condition, the transistor M
2
becomes diode connected. It should be noted that the capacitance Cb is very small, being approximately one twentieth the capacitance Ce; accordingly, the loss of charge incurred by shorting the nodes
1
and
2
will be trivial.
With this circuit design, a threshold loss at every stage is no longer experienced. However, at low supply voltages, or with transistors exhibiting a high body effect, the circuit performance is bound to deteriorate considerably.
In fact, the voltage Fbx(Fbn) may no longer suffice to turn on the horizontal pass transistor (M
1
/M
3
) which allows a charge transfer to occur between the capacitors Cc.
The underlying technical problem of this invention, is to provide a novel voltage booster structure with appropriate structural and functional features to have a higher voltage level transferred more efficiently, as well as to overcome the aforementioned limitations of the prior art.
SUMMARY OF THE INVENTION
The principle on which the disclosed embodiment of this invention stands is to arrange for a transfer of boosted voltage to occur between intermediate stages of the voltage booster, with a first transfer being the equal of one transistor threshold. In this way, the gate of the pass transistor between any two stages can be at the same voltage as the drain voltage only during the phase when said pass transistor is not to transfer charge between the two stages. This may be regarded as being the equivalent of an increase, over the prior art, in the gate voltage of the pass transistor equal to a transistor threshold voltage.
Based on this principle, the technical problem is solved by a voltage booster that includes a pair of additional circuit elements for transferring, onto said internal node, a potential exceeding the voltage at said input node by at least one threshold.
A first circuit element is essentially a MOS transistor having its control terminal connected to the control terminal of said pass transistor, and the second additional circuit element is an auxiliary capacitor having one end connected to a terminal of the first additional element.
The features and advantages of a voltage booster according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings.


REFERENCES:
patent: 4460952 (1984-07-01), Risinger
patent: 4935644 (1990-06-01), Tsujimoto
patent: 5335200 (1994-08-01), Coffman et al.
patent: 5489870 (1996-02-01), Arakawa
patent: 5589793 (1996-12-01), Kassapian
patent: 5821805 (1998-10-01), Jinbo
patent: 6100557 (2000-08-01), Hung et al.

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