CMOS technology high speed digital signal transceiver

Details CMOS technology high speed digital signal transceiver CMOS technology high speed digital signal transceiver

1994-10-28

1997-04-15

Chin, Stephen

Pulse or digital communications

Transceivers

375376, 327159, 331 11, H04B 138, H04L 516

Patent

active

056217552

ABSTRACT:
A high speed digital signal transceiver in CMOS technology, in which the receiver has a clock signal extraction circuit, which is capable of self-aligning on incoming data with no spurious locks. Utilizing the PLL technique, the circuit generates a clock signal locked to the incoming signal utilizing a local oscillator, voltage-controlled by two feedback loops, a main one for frequency and phase corrections and a secondary one for phase correction. Moreover, original circuit solutions for the phase detectors and the low-pass filters are also envisaged.

REFERENCES:
patent: 4298986 (1981-11-01), Hughes
patent: 5015970 (1991-05-01), Williams et al.
patent: 5487093 (1996-01-01), Adresen et al.
GEC Plessey (Semiconductors), SP9970 C HG, 4 pages.
Barry L. Thompson, "A BICMOS Receive/Transmit PLL Pair for Serial Data Communication" 1992 IEEE, 5 pages.

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