CMOS sum select incrementor

Details CMOS sum select incrementor CMOS sum select incrementor

1997-05-05

1999-03-30

Malzahn, David H.

Boots, shoes, and leggings

G06K 750

Patent

active

058896937

ABSTRACT:
A method and apparatus for a CMOS inverter is provided for incrementing a first number by a one, three, or multiple of two. The incrementing unit includes an extract/restore unit for extracting a number of least significant bits from the first number, thereby producing a second number. The number of least significant bits extracted is determined by the incrementing value. The incrementing unit further includes an adjusting unit for adding an adjusting value to the least significant bits extracted from the first number, thereby producing an adjusted least significant bits. The incrementing unit further includes an incrementor block for receiving the second number and incrementing the second number, thereby producing a fourth number. The the extract/restore unit further for restoring the adjusted least significant bits to the fourth number, thereby producing a final result.

REFERENCES:
patent: 5504698 (1996-04-01), Su
patent: 5555517 (1996-09-01), Agrawal et al.
patent: 5682342 (1997-10-01), Suzuki

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