CMOS subtractor

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Details

307471, G06F 742, G06F 750, H03K 1921, H03K 1920

Patent

active

047093463

ABSTRACT:
A subtractor for an N-bit digital number comprising N cascaded cells, each cell being adapted to effect subtraction by two's complement arithmetic and to provide a carry-out signal in accordance with the level of two bits being processed and a carry-in signal.

REFERENCES:
patent: 3084861 (1963-04-01), Roberts
patent: 3257551 (1966-06-01), Gotz et al.
patent: 3766371 (1973-10-01), Suzuki
patent: 3816734 (1974-06-01), Brendzel
patent: 3878986 (1975-04-01), Hirasawa
patent: 4471454 (1984-09-01), Dearden et al.
patent: 4547863 (1985-10-01), Colardelle
patent: 4564921 (1986-01-01), Suganuma
patent: 4592007 (1986-05-01), Ohhashi
patent: 4601007 (1986-07-01), Uya et al.
patent: 4621338 (1986-11-01), Uhlenhoff
Toshiba Review, pp. 27-28, Jan.-Feb. 1970.
Floyd, "Digital Logic Fundamentals, pp. 173-185, 1977, Charles E. Merrill Publishing Co., Columbus Oh.

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