CMOS substrate bias generator having only P channel transistors

Details CMOS substrate bias generator having only P channel transistors CMOS substrate bias generator having only P channel transistors

1983-11-02

1986-04-08

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, H03K 3354, G05F 156

Patent

active

045815461

ABSTRACT:
A CMOS substrate bias generator including a PMOS charge pump and a regulator for controlling the operation of the substrate bias generator. The substrate bias generator further includes an input circuit, a reference circuit to provide a reference voltage, a comparison circuit to compare voltage levels between the input and the reference circuit, and output circuitry to provide a signal from the comparison circuitry to the substrate bias generator. The comparison circuitry further includes hysteresis circuitry tending to preserve voltage at a node in the comparison circuit despite an imbalance between the input circuit and the reference circuit.

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patent: 4455493 (1984-06-01), Morton et al.
Chang, "Substrate Voltage Sensitivity Detector", IBM Tech. Disc. Bull., vol. 21, No. 1, Jun. 1978, pp. 257-258.
Harroun, "Substrate Bias Voltage Control", IBM Tech. Disc. Bull., vol. 22, No. 7, Dec. 1979, pp. 2691-2692.
L. Arzubi, E. Baier, P. Knott and W. Loehlein; "High Performance, Low Power Voltage Doubler"; IBM Technical Disclosure Bulletin, vol. 23, No. 10, Mar. 1981; pp. 4522-4524.
S. C. Chen and S. Park; "Feedback Substrate Bias Generator"; IBM Technical Disclosure Bulletin, vol. 23, No. 5, Oct. 1980; pp. 1930 and 1931.

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