CMOS substrate bias generator

Details CMOS substrate bias generator CMOS substrate bias generator

1984-08-14

1986-12-23

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 307594, 307597, H03L 100

Patent

active

046314210

ABSTRACT:
A generator for producing a negative bias voltage on a semiconductor device employs an on-chip oscillator driving two charge pump circuits. The oscillator produces a frequency inversely related to the negative bias, using a feedback circuit, thus reducing standby current. Each of the charge pumps include a CMOS inverter for controlling the transistor that functions as a diode connection to the ground terminal, producing an efficient charge transfer and speeding up generation of the bias voltage. Both charge pumps are used during power-up so the bias is rapidly increased to the operating level, then one is turned off to reduce current drain. A shunt circuit prevents CMOS latch-up during power-UP by coupling the substrate node to ground, preventing forward bias of N+ source/drain regions with respect to P substrate.

REFERENCES:
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4388537 (1983-06-01), Kanuma
patent: 4455628 (1984-06-01), Ozaki et al.
patent: 4471290 (1984-09-01), Yamaguchi
patent: 4473758 (1984-09-01), Huntington
patent: 4547682 (1985-10-01), Bialas, Jr. et al.
patent: 4553047 (1985-11-01), Dillinger et al.
Harroun, "Substrate Bias Voltage Control", IBM T.D.B., vol. 22, No. 7, Dec. 1979, pp. 2691-2692.

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