CMOS structure fabrication

Details CMOS structure fabrication CMOS structure fabrication

1991-02-04

1992-10-13

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

357 42, 437 44, 437 57, 437 59, J01L 21336

Patent

active

051549468

ABSTRACT:
A method of fabricating a CMOS structure that may be integrated into a BICMOS process flow includes forming N and P type doped wells in an isolation module. A first conformal nitride layer is formed on the surface of the isolation module and portions of the nitride layer disposed over the doped wells are removed. After forming a gate oxide layer on the doped wells, a conformal polysilicon layer is formed and doped on the surface of the structure. The conformal polysilicon layer is etched into gate electrodes which are used as a mask for the self-aligned implant of first portions of source and drain regions in the doped wells. Dielectric spacers abutting the edges of the gate electrodes are formed and the implantation of second portions of the source and drain regions is self-aligned to the dielectric spacers. Following the formation of a conformal nitride layer and a conformal oxide layer, the structure is planarized and source, drain and gate contacts are formed.

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