Patent
1975-11-13
1980-05-13
James, Andrew J.
357 41, 357 44, 357 88, 357 89, 357 90, H01L 2702
Patent
active
042031265
ABSTRACT:
CMOS device and method utilizing a retarded electric field for reducing the current gain in the base region of parasitic transistors in the device. A buried layer is utilized in the base region of the parasitic transistor, and the resistivities of the buried layer and substrate are chosen to reduce both NPN and PNP betas and also to reduce the distributed resistance shunting the P+N and N+P junctions, thereby increasing the level of current required to produce latch-up in the device.
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RCA Technical Notes; Non Latching Integrated Circuits by W. J. Dennehy; Feb. 1971, pp. 1 to 4. _
Electronics; Getting the Most Out of CMOS Devices for Analog Switching Jobs; by E. Thibodeaux; Dec. 1975, pp. 69-74. _
IBM Technical Disclosure Bulletin; by James, vol. 16 No. 6 Nov. 1973, p. 1998. _
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VanLoon Paul G. G.
Yim Ernest W.
James Andrew J.
Siliconix Inc.
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