Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock
Patent
1991-04-05
1993-12-21
Zazworsky, John
Electrical transmission or interconnection systems
Personnel safety or limit control features
Interlock
307279, 307530, H03K 524, H03K 3037, H03K 3356
Patent
active
052723950
ABSTRACT:
An all CMOS voltage comparator circuit which incorporates a strobed latch. A strobe signal precharges the entire circuit to a known state which is independent of the input voltages and in which substantially no static current is drawn. Under static conditions after the circuit has been strobed, the source coupled pair is virtually disconnected from the supply voltage(s) and draws almost no current, as well. When the circuit is strobed, a source coupled FET pair amplifies the differential input signal, with positive feedback provided through a pair of cross coupled PMOS load transistors, as well as cross coupled NMOS cascode transistors. The source coupled pair feeds a pair of output buffers, or drivers, whose FETs are sized such that a "low" voltage level is generated on both outputs until the source-coupled pair resolves the input voltage difference (i.e., the differential input voltage exceeds the switching threshold). At that time, the outputs become complementary digital levels and are usable.
REFERENCES:
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patent: 5032744 (1991-07-01), Liu
patent: 5034636 (1991-07-01), Reis et al.
patent: 5055720 (1991-10-01), Tiede
patent: 5057718 (1991-10-01), Proebsting
Wu, Jieh-Tsorng and Wooley, Bruce A., "A 100-MHz Pipelined CMOS Comparator", IEEE Journal of Solid-State Circuits, vol. 23, No. 6, Dec. 1988, pp. 1379-1385.
Yukawa, Akira, "A CMOS 8-Bit High-Speed A/D Converter IC", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 3, Jun. 1985, pp. 775-779.
Steyaert, M. and Comino, V., "High-Speed Accurate CMOS Comparator", Electronic Letters, 4th Aug. 1988, vol. 24, No. 16, pp. 1027-1028.
Analog Devices Inc.
Zazworsky John
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