CMOS SRAM cell configured using multiple-gate transistors

Details CMOS SRAM cell configured using multiple-gate transistors CMOS SRAM cell configured using multiple-gate transistors

2005-03-08

2005-03-08

Smoot, Stephen W. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

Having specific type of active device

C257S208000, C257S369000, C257S410000

Reexamination Certificate

active

06864519

ABSTRACT:
A complementary metal-oxide-semiconductor static random access memory cell that is formed by a pair of P-channel multiple-gate field-effect transistors (P-MGFETs), a pair of N-channel multiple-gate field-effect transistors (N-MGFETs), a second pair of N-MGFETs that has a drain respectively connected to a connection linking the respective drain of the N-MGFET of the first pair of N-MGFET to the drain of the P-MGFET of the pair of P-MGFETs; a pair of complementary bit lines, each respectively connected to the source of the N-MGFET of the second pair of N-MGFETS; and a word line connected to the gates of the N-MGFETs of the second pair of N-MGFETs.

REFERENCES:
patent: 5317178 (1994-05-01), Wu
patent: 5814895 (1998-09-01), Hirayama
patent: 6157061 (2000-12-01), Kawata
patent: 6380024 (2002-04-01), Liaw
patent: 6573549 (2003-06-01), Deng et al.
patent: 20030042528 (2003-03-01), Forbes
patent: 20030178670 (2003-09-01), Fried et al.

Affiliated with

Also associated with

Rating

CMOS SRAM cell configured using multiple-gate transistors does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS SRAM cell configured using multiple-gate transistors, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS SRAM cell configured using multiple-gate transistors will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3377453