CMOS Source/drain implant process without compensation of polysi

Details CMOS Source/drain implant process without compensation of polysi CMOS Source/drain implant process without compensation of polysi

1981-10-15

1983-12-13

Roy, Upendra

Metal treatment

Compositions

Heat treating

29571, 29576B, 148187, 357 42, 357 91, H01L 21263, H01L 2126

Patent

active

044203446

ABSTRACT:
CMOS source/drain regions of both conductivity types are formed using only a single masking step. One dopant is applied to both types of source/drain regions, and a second dopant is applied at a much higher dose and energy to only one type of source/drain region. Preferably, boron and arsenic are used as the dopants in silicon, since the cooperative diffusion effect causes the boron in the counterdoped source/drain regions to be entirely contained within the arsenic diffusion.
To avoid the erratic etching characteristics of heavily-doped polysilicon under chloro-etch, the patterned photoresist used to pattern the gates and gate-level interconnects is left in place during the P+ source/drain implant. Thus, moderately doped N-type polysilicon may be used, since it is not exposed to compensation by the P+ implant. Since no P+ source/drain mask is required, no double-level photoresist structure is created, and there is consequently no obstacle to reworks. In addition, positive resists may be used in practicing the present invention.

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patent: 4314857 (1982-02-01), Aitken
patent: 4335504 (1982-06-01), Lee

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