CMOS SOS With narrow ring shaped P silicon gate common to both d

Details CMOS SOS With narrow ring shaped P silicon gate common to both d CMOS SOS With narrow ring shaped P silicon gate common to both d

1978-09-21

1981-06-02

Larkins, William D.

29571, 357 23, 357 49, 357 59, H01L 2712, H01L 2978, H01L 2122, H01L 2128

Patent

active

042714222

ABSTRACT:
A layer of polycrystalline silicon is coated with a masking layer leaving at least one edge of the silicon layer exposed. A P-type dopant is diffused into the exposed edge of the silicon layer so that the dopant diffuses laterally along the silicon layer a desired distance. The masking layer is then removed and the undoped portion of the silicon layer is removed by an etchant which does not etch the doped portion of the silicon layer. This leaves the narrow strip of the doped silicon which can be used as the gate electrode of an MOS transistor and/or as an interconnection in an integrated circuit. Since the lateral diffusion of the dopant can be accurately controlled, narrow strips of the doped silicon can be achieved.

REFERENCES:
patent: 3890632 (1975-06-01), Ham et al.
patent: 4026740 (1977-05-01), Owen
patent: 4124933 (1978-11-01), Nicholas

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