CMOS SOI contact integrity test method

Details CMOS SOI contact integrity test method CMOS SOI contact integrity test method

1998-06-25

2001-01-16

Brown, Glenn W. (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

C324S762010

Reexamination Certificate

active

06175245

ABSTRACT:

FIELD OF THE INVENTION
This invention generally relates to a method of testing integrated circuit (IC) chips, lore particularly, it relates to a method of ensuring that probes are in good electrical contact with a semiconductor device lacking a resistive or diode electrical path that can be contacted. Even more particularly, it relates to a method of testing IC chips in which devices on the chips have back insulators, such as silicon-on-insulator (SOI) IC chips that prevent formation of diodes to substrate.
BACKGROUND OF THE INVENTION
As a first step in testing an integrated circuit chip probe contact to the chip is usually checked to ensure that good electrical connection has been achieved. FIG.
1
a
shows a circuit diagram and FIG.
1
b
shows a cross sectional view of an inverter type of input receiver
18
on a chip formed on a conventional bulk silicon semiconductor wafer. Input pad
20
of integrated circuit chip
22
is connected to gates
24
a
,
24
b
of inverter pair
26
of complementary CMOS transistors, including PFET
28
a
and NFET
28
b
that make up receiver
18
. Input pad
20
and gates
24
a
,
24
b
are also connected to diffusion
30
in p-substrate substrate
32
that forms ESD protect diode
34
. Probe contact to input pad
20
of chip
22
is easily checked by a technique such as forcing a voltage between pad and substrate probes (not shown) to forward bias protect diode
34
, and measuring the resulting current at either probe. Where chip pads on bulk silicon substrates are connected to semiconductor substrate
32
through a diffusion such as diffusion
30
of ESD protect diode
34
, contact is most easily checked by looking for the current-voltage characteristic of a forward biased diode between chip pad
10
and substrate
32
.
However. some semiconductor technologies save chip real estate by providing inputs without protect devices, and these technologies have essentially floating gates, making the contact check difficult. Other technologies use protect devices that are not easily turned on, such as snap back diodes, and this similarly hinders the contact check. In addition, devices fabricated on material having a back insulator, such as SOI CMOS pair
40
of
FIG. 2
, are isolated from semiconductor substrate
32
by back insulator
42
. CMOS SOI transistors
24
a
′ and
24
b
′ are formed in isolated wells
44
a
,
44
b
, and there is generally no well contact brought out. Input pad
20
′ of the SOI chip is therefore not electrically connected to another available pad through a device, such as a resistor or diffusion, that would enable checking probe contact.
In cases where there has been no diode to forward bias or where no substantial current could be forced between an input pad and the substrate or between any other two pads, there has been no way to distinguish probe contact difficulties from internal causes of chip failure. The solution to this uncertainty has been to simply push harder on the probes and test again. However, a better solution is needed that provides a way to check whether probes are properly electrically connected to chip pads and to determine which of the many probes is not electrically connected, and this solution is provided by the following invention.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide an improved method of checking individual probes and determining whether each probe is actually electrically contacting a pad of a chip.
It is another object of the present invention to provide a method of checking that probes are contacting a chip having input pads tied to floating gates.
It is another object of the present invention to provide a method of checking that probes arc contacting a chip having a back insulator, such as an SOI chip.
It is a feature of the present invention that an individual contact is checked by measuring current drawn through other contacts to the chip.
It is a feature of the present invention that an individual contact is checked by measuring Idd current.
It is an advantage of the present invention that contact is checked without requiring any design or processing steps or added cost in integrated circuit manufacture or test.
It is an advantage of the present invention that false fails as a result of bad contact are avoided when testing chips, such as SOI chips or chips having essentially floating input pads, and the specific probe or probes having a contact problem can be identified for corrective action.
These and other objects, features, and advantages of the invention are accomplished by a method of testing, comprising the steps of:
(a) providing a CMOS integrated circuit chip comprising a plurality of I/O pads for external contact said I/O pads connected to gates of transistors:
(b) providing a logical high or a logical low voltage to all but a first of said plurality of pads and applying an intermediate voltage level exclusively to said first of said pads to partially turn on a first of said transistors; and
(c) measuring chip Idd standby current while said intermediate voltage is being provided to said first pad.


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patent: 5986461 (1999-11-01), Kalb, Jr.
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