CMOS sidewall oxide-lightly doped drain process

Details CMOS sidewall oxide-lightly doped drain process CMOS sidewall oxide-lightly doped drain process

1986-03-27

1992-08-25

Wilczewski, M.

Fishing, trapping, and vermin destroying

437 34, 437 57, 437 29, 437 30, 357 233, H01L 21336

Patent

active

051418908

ABSTRACT:
A CMOS process wherein lightly doped drain extensions are fabricated in the N-channel devices without any additional masking steps. The present invention requires a specific sequence of steps, after all steps through patterning of the polysilicon gate level have been completed: first, a light shallow N-type implant is performed overall. Next, oxide is deposited overall. Second, photoresist is patterned according to the P-type source/drain mask. The exposed conformal oxide is etched away completely, and the P-type source/drain implant is performed. Third, after the P-type source/drain photoresist is removed, the conformal oxide is anisotropically etched to leave sidewall oxide filaments, the N+ source/drain masking layer is applied, and the N+ source/drain implant is performed. This process results in short lightly doped drain extensions on the source/drain regions of the N-type devices only and not of the P-type devices. Alternatively, the conformal oxide is not deposited until after the pt source/drain resist is removed, so that the PMOS devices also have sidewall oxides (for better topography), but not lightly doped drain extension.

REFERENCES:
patent: 4382827 (1983-05-01), Romano-Moran et al.
patent: 4385947 (1983-05-01), Halfacre et al.
patent: 4433468 (1984-02-01), Kawamata
patent: 4442591 (1984-04-01), Haken
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4590663 (1986-05-01), Haken
patent: 4657602 (1987-04-01), Henderson, Sr.
patent: 4753898 (1988-06-01), Parrillo et al.

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