CMOS shift register with complementary refresh pass gates and bu

Details CMOS shift register with complementary refresh pass gates and bu CMOS shift register with complementary refresh pass gates and bu

1990-10-25

1992-10-27

Heyman, John S.

Electrical pulse counters, pulse dividers, or shift registers: c

Shift register

Particular transfer means

377105, 377117, G11C 1928, H03K 2344

Patent

active

051596164

ABSTRACT:
The improved CMOS shift register consists of a series of alternating PMOS and NMOS pass gates driven by a single clock signal. Each gate consists of either one or more PMOS transistor(s), or one or more NMOS transistor(s). When the clock signal goes low, the PMOS gates turn on and pass bit values. At the same time the adjacent NMOS gates, which are driven by the same low clock signal, shut off and prevent the passed bit values from traveling any further. The bit values are thus held between adjacent PMOS and NMOS gates. When the clock signal next goes high, the NMOS gates turn on and pass the held bit values while the PMOS gates driven by the same high clock shut off. The gates are connected by circuitry which essentially holds the bit values passed through the first associated gate until they are passed through the second associated gate. The shift register may also include gated or non-gated refresh circuitry, which operates to maintain a passed bit value. The refresh circuitry may include gates which are the complements of the associated pass gates, with all the gates driven by the same clock signal.

REFERENCES:
patent: 4084107 (1978-04-01), Ohba et al.
patent: 4250406 (1981-02-01), Alaspa
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4571504 (1986-02-01), Iwamoto et al.
patent: 4705965 (1987-11-01), Stuyt
IBM Tech. Disclosure Bul. vol. 12 No. 12 May 1970 "Complementary FET Dynamic Shift Register Using a Single Phase Line" by Gaensslen et al.

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