CMOS sensor having analog delay line for image processing

Details CMOS sensor having analog delay line for image processing CMOS sensor having analog delay line for image processing

1999-09-15

2004-03-16

Garber, Wendy R. (Department: 2612)

Television

Camera, system and detail

Solid-state image sensor

C348S304000

Reexamination Certificate

active

06707496

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to metal oxide semiconductor (MOS) image sensors and, more particularly, an analog delay line for a MOS image sensor.
BACKGROUND OF THE INVENTION
Integrated circuit technology has revolutionized various fields including computers, control systems, telecommunications, and imaging. In the field of imaging, the charge coupled device (CCD) sensor has made possible the manufacture of relatively low-cost and small hand-held video cameras. Nevertheless, the solid-state CCD integrated circuits needed for imaging are relatively difficult to manufacture, and therefore are expensive. In addition, because of the differing processes involved in the manufacture of CCD integrated circuits relative to MOS integrated circuits, the signal processing portion of the imaging sensor has typically been located on a separate integrated chip. Thus, a CCD imaging device includes at least two integrated circuits: one for the CCD sensor and one for the signal processing logic.
Some of the further drawbacks of CCD technology are discussed in “Active Pixel Sensors—Are CCD's Dinosaurs?” by E. R. Fossum, Proceedings of the SPIE—The International Society for Optical Engineering, Vol. 1900, 1993, pp. 2-14. As stated therein, “[a]lthough CCDs have become a technology of choice for present-day implementation of imaging and spectroscopic instruments due to their high-sensitivity, high quantum efficiency, and large format, it is well-known that they are a particularly difficult technology to master. The need for near-perfect charge transfer efficiency makes CCDs (1) radiation ‘soft,’ (2) difficult to reproducibly manufacture in large array sizes, (3) incompatible with the on-chip electronics integration requirements of miniature instruments, (4) difficult to extend the spectral responsivity range through the use of alternative materials, and (5) limited in their readout rate.”
An alternative low-cost technology to CCD integrated circuits is the metal oxide semiconductor (MOS), integrated circuit. Not only are imaging devices using MOS technology less expensive to manufacture relative to CCD imaging devices, for certain applications MOS devices are superior in performance. For example, the pixel elements in a MOS device can be made smaller and therefore provide a higher resolution than CCD image sensors.
Examples of MOS imaging devices are detailed in “A ¼ Inch Format 250 K Pixel Amplified MOS Image Sensor Using CMOS Process” by Kawashima et al., IEDM 93-575 (1993), and “A Low Noise Line-Amplified MOS Imaging Devices” by Ozaki et al., IEEE Transactions on Electron Devices, Vol. 38, No. 5, May 1991. In addition, U.S. Pat. No. 5,345,266 to Denyer, titled “Matrix Array Image Sensor Chip,” describes a MOS image sensor. The devices disclosed in these-publications provide a general design approach to MOS imaging devices. In addition, MOS approaches to color imaging devices are described in “Color Filters and Processing Alternatives for One-Chip Cameras,” by Parulski, IEEE Transactions on Electron Devices, Vol. ED-32, No. 8, August 1985, and “Single-Chip Color Cameras With Reduced Aliasing” by Imaide et al., Journal of Imaging Technology, Vol. 12, No. 5, October 1986, pp. 258-260.
In the movement from CCD- to MOS-based implementations that can be fabricated on a single MOS chip, certain concepts from the CCD technology have not transferred smoothly. One example is related to the external CCD-delay line that is still used in many image processors to obtain the necessary signals from two rows of pixels simultaneously. The need to process two rows of pixels simultaneously is related to the processing of signals from complementary color filter patterns, as is described in more detail below.
In most solid-state color image sensors, a complementary color filter pattern is used. Arrays of pixels may be made to detect color by being covered with a regular pattern of color filter patches, known as a color filter pattern. The filter patches can be fabricated directly on the sensor or on a transparent substrate which is later cemented to the chip. Color filter patterns may include colors such as red (R), green (G), blue (B), yellow (Ye), cyan (Cy) and magenta (Mg). The pixels beneath the color filter pattern emit signals when they are exposed to the type of light indicated by the color filter patch. Thus, a red signal could be obtained from a pixel beneath a red filter patch, a blue signal could come from a pixel beneath a blue filter patch, and so on.
However, some image sensors do not obtain the standard red, green and blue signals from red, green and blue filtered pixels. Instead, they use combinations of other colors to obtain the standard ones. For example, red (R) can be formed according to the equation R=(W+Ye)−(G+Cy), where the color filter pixel signals are W=white, Ye=yellow, G=green, and Cy=cyan. In cases such as this, the four pixel signals being processed are obtained from a 2×2 block of one of each type of pixel sensor, rather than a 1×4 row of pixel sensors which would tend to distort the color image. The 2×2 block presents a problem for standard pixel scanning methods because standard methods scan each row, one at a time. In contrast, the 2×2 block of pixels comes from sections of two separate rows. Thus, the system cannot process the data as it scans each row. It must wait until the next row is also scanned to obtain the remaining information that it needs, and it must somehow save the data from the previous row until it does so.
Just as the color signals in such cases can be a combination of the signals from a 2×2 pixel block, the chrominance signal, which correlates to the color of the image, is also sometimes obtained from a combination of signals from pixels in two separate rows. In fact, this is the case for the chrominance signal in many systems, even those in which R, G and B filters are used to obtain the color signals directly. Therefore, it is required in such systems to somehow have the data from two separate rows available at the same time so that the required combinations can be processed.
A standard method for making the data from two separate rows available at the same time is to use a delay line. The delay line holds the data from one row until the next row can be scanned to provide the needed information. One simple type of delay line is a digital delay line. The digital delay line stores digital values representative of the pixel signals from a given row. Digital delay lines are commonly used in MOS imaging devices. However, in order to use a digital delay line, the pixel signals must necessarily be first converted to digital values before they are stored in the digital delay line. One of the problems with converting the pixel signals to digital values at this early stage, is that the analog-to-digital processing requires a significant amount of power. This is an undesirable characteristic in certain implementations of imaging devices.
An alternative to a digital delay line that has been used in most prior art CCD devices is an analog CCD delay line.
FIG. 1
illustrates a general CCD delay line of the prior art. As illustrated in
FIG. 1
, signals from a sensor array are received via a signal line V
0
by a CCD delay line
10
. The CCD delay line
10
delays the pixel signals as it takes time for the signals to cascade down the cells of the CCD delay line. The CCD delay line is controlled so that after a first row of pixels has been read into the CCD delay line, the signal from the first pixel of the first row is read out from the CCD delay line on the signal line V
1
at the same time that the pixel signal from the first pixel of the second row is being received on the signal line V
0
. In this manner, the signal processing circuitry
12
receives the signals from adjacent pixels in two different rows at the same time. In this manner, a 2×2 pixel block may be obtained for signal processing, as described above.
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