Patent
1990-10-01
1992-06-23
Wojciechowicz, Edward J.
357 42, 357 41, H01L 2702
Patent
active
051247780
ABSTRACT:
A CMOS semiconductor integrated circuit device has an n-(p-)MOS element formed on a p-(n-)type semiconductor substrate and a p-(n-)MOS element formed on an n-(p-)type well region. A substrate potential wiring for providing a substrate potential to the p-(n-)type semiconductor substrate and a source potential wiring connected to the source region of the n-(p-)MOS are provided physically independently from each other, and such potential wiring and such source potential wiring are connected with each other with a resistor being interposed therebetween. Thus, the current which flows in transistors during the operating state of related circuits integrated in the substrate is prevented from flowing into the substrate thereby eliminating any such fluctuations of the substrate potential as may otherwise be caused by the operation of the circuits.
REFERENCES:
patent: 4862241 (1989-08-01), Ashida et al.
NEC Corporation
Wojciechowicz Edward J.
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