Patent
1991-02-26
1992-01-21
Wojciechowicz, Edward J.
357 52, 357 54, 357 55, H01L 2702
Patent
active
050831798
ABSTRACT:
In a CMOS semiconductor integrated circuit device, an element isolating insulation film is formed on an N-type epitaxial layer deposited on an N-type semiconductor substrate, and two CMOS circuits are arranged in a region surrounded by the element isolating insulation film. Each of the CMOS circuits includes a P-channel MOS transistor and an N-channel MOS transistor. The source region of the P-channel MOS transistor of one of the CMOS circuits at the final stage is connected to a power source through a first feed path constituted of a metal wiring layer formed on the semiconductor substrate. The source of the P-channel MOS transistor of the other CMOS circuit is connected to the power source through the semiconductor substrate, the epitaxial layer, and an N-type semiconductor region formed on the epitaxial layer.
REFERENCES:
patent: 4969029 (1990-11-01), Ando et al.
Chong Teek F.
Ito Takahiro
Kabushiki Kaisha Toshiba
Wojciechowicz Edward J.
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