CMOS semiconductor device

Details CMOS semiconductor device CMOS semiconductor device

1986-09-30

1988-04-26

Edlow, Martin H.

357 49, 357 55, 357 50, 357 2311, H01L 2978, H01L 2702, H01L 2906, H01L 2712

Patent

active

047408278

ABSTRACT:
In the CMOS semiconductor device having an epitaxial layer, a trench with an appropriate depth is formed in the vicinity of a boundary between a range in which a MOS transistor is formed and a well range in which another MOS transistor is formed; the inner wall surface of the trench is covered with a thermal oxide film; and the trench is buried with a semiconductor substance, so that two CMOS transistors can be electrically isolated by the trench to increase the latch-up holding voltage beyond a supply voltage (e.g. 5 v). Therefore, the latch-up proof resistance can be increased to protect the device from noise which otherwise would break the device. Further, the trench depth is shallower than the low impurity atom concentration layer (epitaxial layer) or 3 .mu.m but deeper than a value obtained by subtracting 2 .mu.m from the above thickness or 3 .mu.m.

REFERENCES:
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patent: 4477310 (1984-10-01), Park et al.
patent: 4578128 (1986-03-01), Mundt et al.
patent: 4613885 (1986-09-01), Haken
patent: 4647957 (1987-03-01), Coquin et al.
R. D. Rung et al., "Deep Trench Isolated CMOS Devices", IEEE International Electron Devices Meeting, pp. 237-240, (Dec. 1982).
Y. Niitsu et al., "Latchup-Free CMOS Structure Using Shallow Trench Isolation", IEEE International Electron Devices Meeting, pp. 509-512, (Nov. 30, 1985).

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