CMOS Schmitt trigger

Details CMOS Schmitt trigger CMOS Schmitt trigger

1985-08-14

1987-10-27

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307279, 307451, 307576, 307579, 307585, H03K 329, H03K 326, H03K 19094, H03K 17687

Patent

active

047032014

ABSTRACT:
The circuit comprises a first pair of n and p-channel MOSFETS, T1 and T2, whose gates are connected to form the trigger input, whose sources are commoned at node B and whose drains are respectively connected to the positive supply rail (3) and the ground rail (4). Node B is connected to the input to a standard CMOS inverter comprising second p and n-channel MOSFETS T3 and T4. A third p-channel MOSFET T5 has its gate connected to the output of the inverter, its source connected to the positive supply rail and its drain connected to node B. A third n-channel MOSFET T6 also has its gate connected to the output of the inverter, its drain connected to node B, and its source connected to the ground rail.
T5 and T6 act as pull-up and pull-down MOSFETS for the node B to ensure that T4 and T3 are respectively turned hard on when the input at A is high or low.
The threshold for response to a high going signal at input A is determined by the ratio of the sizes of T6 and T1. Similarly, the threshold for response to a low going signal is determined by the ratio of the sizes of T5 and T2.

REFERENCES:
patent: 79522 (1881-06-01), Seikosha
patent: 3823330 (1974-07-01), Rapp
patent: 4080539 (1978-03-01), Stewart
patent: 4258272 (1981-03-01), Huang
patent: 4406957 (1983-09-01), Atherton
Principles of CMOS VLSI Design, by Weste & Eshraghian, pp. 37-40.
Analysis and Design of Digital Integrated Circuits, by Hodges & Jackson, pp. 39-49.

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