CMOS row decoder circuit for use in row and column addressing

Details CMOS row decoder circuit for use in row and column addressing CMOS row decoder circuit for use in row and column addressing

1987-09-09

1988-11-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307463, 307481, 365203, H03K 19096

Patent

active

047884576

ABSTRACT:
A CMOS row decoder circuit in which a row decoder for selecting a single word line from a memory cell array and a column decoder for selecting a single bit line can use in common an internal address signal transmission line. The row decoder circuit comprises a series of MOSFETs of a first conductivity type which is turned on or off in response to address signals selected from external address signals, a second MOSFET of a second conductivity type provided between a power supply potential and the series of MOSFETs and having a gate receiving a first timing signal for providing decoding timing of the address signals, a third MOSFET of the first conductivity type provided between the series of MOSFETs and the second MOSFET and having a gate receiving a first operation timing signal, a fourth MOSFET which is turned on or off in response to a second operation timing signal for transmitting the potential of a node of the second MOSFET and the third MOSFET, and a fifth MOSFET having a gate receiving an output of the fourth MOSFET for transmitting a word line driving signal to a corresponding word line.

REFERENCES:
patent: 4200917 (1980-04-01), Moench
patent: 4275312 (1981-06-01), Saitou et al.
patent: 4309629 (1982-01-01), Kamuro
patent: 4446386 (1984-05-01), Kurafuji
patent: 4571510 (1986-02-01), Seki et al.
patent: 4700086 (1987-10-01), Ling et al.
patent: 4730133 (1988-03-01), Yoshida
IEEE, Katsutaka Kimura et al, "Power Reduction Techniques in Megabit DRAMS's", vol. SC-21, No. 3, Jun. 1986, pp. 381-389.
Hafani, "Bit Line Discharge Circuit for NAND Logic Read-Only Storage Arrays", IBM T.D.B., vol. 23, No. 7B, Dec. 1980, pp. 3181-3182.
Lane et al, "FET Parallel Decoder", IBM T.D.B., vol. 11, No. 5, Oct. 1968, p. 444.

Affiliated with

Also associated with

Rating

CMOS row decoder circuit for use in row and column addressing does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS row decoder circuit for use in row and column addressing, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS row decoder circuit for use in row and column addressing will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-365538