CMOS reference voltage generation

Details CMOS reference voltage generation CMOS reference voltage generation

1987-07-13

1989-06-06

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307355, 307494, 307497, 307260, 323315, 330253, 330261, H03K 3023, H03K 3353, H03K 3013, H03K 17687

Patent

active

048374598

ABSTRACT:
A process insensitive reference voltage generator includes a first and second identical FET devices coupled in a parallel configuration with a first biasing network, of FET devices, interconnecting the substrate terminal of the first FET device to a first node formed between a positive voltage supply and ground potential. The control terminal is connected to a second node whose voltage potential is different from that of the first node. The substrate terminal of the second FET device is connected to the source terminal. The source terminals of both FET devices are connected to the respective input terminals of an operational amplifier whose output is connected to the control terminal of said second FET device.

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