CMOS read-only memory with static operation

Details CMOS read-only memory with static operation CMOS read-only memory with static operation

1988-09-16

1990-05-22

Moffitt, James W.

Static information storage and retrieval

Read only systems

Semiconductive

365190, 36518911, 307279, G11C 700

Patent

active

049282611

ABSTRACT:
A CMOS read-only memory with static operation having at least one individually activatable row (R.sub.n) and a plurality of main columns (C.sub.1, C.sub.2) which cross the rows, each crossing including pull-down cell (N.sub.1) corresponding to a logical "0" or a pull-down cell (N.sub.2) corresponding to a logical "1", the pull down cells controlled the individually activatable row, the main columns leading to the supply voltage through a respective pull-up transistor (P.sub.1, P.sub.2). To each main column, there is an associated auxiliary column (CX.sub.1, CX.sub.2) which is also connected to the supply voltage through a respective pull-up transistor (PX.sub.1, PX.sub.2). The gates of the pull-up transistors of the main columns are connected to a respective auxiliary column, and the gates of the pull-up transistors of the auxiliary columns are connected to a respective main column.

REFERENCES:
patent: 4165538 (1979-08-01), Kitamura
patent: 4389705 (1983-06-01), Sheppard
patent: 4695979 (1987-09-01), Tuvell et al.
patent: 4811301 (1989-03-01), Houston
patent: 4823319 (1989-04-01), Pfennings

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