CMOS read only memory with programming at the second metal layer

Details CMOS read only memory with programming at the second metal layer CMOS read only memory with programming at the second metal layer

1995-04-21

1996-05-14

Nelms, David C.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257211, 365 94, 365104, H01L 23485

Patent

active

055170617

ABSTRACT:
A CMOS ROM is fabricated and programmed using a two-metal fabrication process which is substantially equivalent to a conventionals CMOS polysilicon gate manufacturing technique so that the CMOS ROM is advantageously fabricated in the same process steps that are used to fabricate the other, non-ROM circuits on an integrated circuit chip. In this method, multiple bit-lines in a first metal layer are formed which overlie a substrate containing the array of transistors. The bit-lines are connected to drain regions of the transistors. A dielectric insulating layer is formed over the substrate and the bit-lines and the dielectric insulating layer is perforated by vias which allow connecting to the first metal layer. Multiple word-lines and multiple reference voltage lines are formed in a second metal layer overlying the dielectric insulating layer. Either a word-line or a reference voltage line is programmably selected to connect to the gate of a transistor for each transistor of the multiple transistors.

REFERENCES:
patent: 4326329 (1982-04-01), McElroy
patent: 4384399 (1983-05-01), Kuo
patent: 4390971 (1983-06-01), Kuo
patent: 5294837 (1994-03-01), Takase et al.
patent: 5300814 (1994-04-01), Matsumoto et al.
patent: 5459355 (1995-10-01), Kreifels

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