CMOS RAM with no latch-up phenomenon

Details CMOS RAM with no latch-up phenomenon CMOS RAM with no latch-up phenomenon

1983-02-22

1986-12-09

Carroll, J.

357 231, 357 41, 357 88, H01L 2978, H01L 2702

Patent

active

046283404

ABSTRACT:
A complementary-symmetry metal-oxide semiconductor device is made of a semiconductor substrate of a first conductivity type and well regions of a second conductivity type formed in the surface region of the semiconductor substrate. The well regions consist of a first well region and a second well region having a lower resistance per unit area than the first well region. An input-output peripheral circuit is formed of the second well region and the substrate. An internal circuit is formed of the first well region and the substrate.

REFERENCES:
patent: 3916430 (1975-10-01), Heumer et al.
patent: 4229756 (1980-10-01), Sato et al.
patent: 4233672 (1980-11-01), Suzuki et al.
patent: 4314857 (1982-02-01), Aitken
Y. Sakai et al., "High Packing Density High Speed CMOS (Hi-CMOS) Device Technology" Japanese Journal of Applied Physics, vol. 18 (1979), Supplement 18-1, pp. 73-78.

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