CMOS-RAM memory in a gate array arrangement

Details CMOS-RAM memory in a gate array arrangement CMOS-RAM memory in a gate array arrangement

1989-11-06

1991-07-30

Moffitt, James W.

Static information storage and retrieval

Format or disposition of elements

365156, 365181, G11C 502, G11C 506

Patent

active

050364871

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

The invention is directed to a CMOS-RAM memory in a gate array arrangement composed of seven transistor basic cells wherein a memory cell can be realized with a basic cell.
Gate array arrangements are known (for example, Hitachi Review, Vol. 33 (1984) No. 5, Pages 261-266). In such gate array arrangements, regions are provided on a chip in a specific arrangement in which basic cells are realized. The basic cells are composed of n-channel and p-channel transistors that are arranged in the regions in a specific way. A basic cell can be tailored for realizing a basic function by connecting the n-channel and p-channel transistors per basic cell and, for example, it can be given a logical function or a storing function. It derives from Hitachi Review that was cited above that a basic cell can be composed of, for example, ten transistors that are connected such to one another such that a RAM memory cell having an input or two inputs arises. For example, a logic function, for example, a NAND function, can be realized by other connections of the transistors in a basic cell.
The realization of memories having different capacities was heretofore achieved in various ways. Bistable circuits were employed for low-capacity storing structures. These were composed of a plurality of gates and therefore require a relatively great number of basic cells of a gate array for storing an informational unit. High-capacity memories were realized in that a memory block having a defined capacity and designed as a general cell was integrated in the core region of the chip. As a result the capacity of a memory can only be selected in steps of the memory capacity of this general cell. The area reserved for the general cells can thus only be used for the memory, and not for other logical functions.


SUMMARY OF THE INVENTION

The object underlying the invention is comprised in reciting a RAM memory whose memory cells are composed of seven transistor basic cells and whose size can be arbitrarily adapted to customer demands.
The foregoing object is achieved by providing a CMOS-RAM memory on a gate array arrangement composed of seven transistor basic cells wherein one memory cell can be realized with one basic cell, comprising: the word line decoder containing, per row of memory cells, a decoder sub-circuit realized with basic cells for generating a word line signal from a part of an address signals; area, the drive circuit providing, per row of memory cells, a drive sub-circuit realized with a basic cells for generating a write signal in inverted and non-inverted forms from the word line signal and a selection signal; and memory area at a different side thereof at a column end.
Thus, only one basic cell is used for realizing one or more main memory areas for every memory cell. The circuits required for selection, for reading and writing information are then arranged around the main memory areas. These circuits are likewise realized exclusively with the assistance of the basic cells. When a main memory area is to be added or when a main memory area is to be enlarged, then this is possible in a simple way. Additional basic cells merely have to be provided for the memory cells, these being either arranged in a previous main memory area or an entire main memory area attached next to the previous main memory area. The position of the circuits required for the drive and selection of the memory cells, these circuits being grouped around the main memory areas, is thereby hardly affected. Moreover, the possible memory configurations can be freely selected. When the maximum memory capacity amounts, for example, to 16K, then the possible memory configuration can amount to either 512 words times 32 bits through 4096 words times 4 bits. It is expedient to select the word width equal to or greater than 4 bits, whereby the word width can be expanded in steps of 1 bit.
The invention is set forth in greater detail in the following detailed description of the presently preferred embodiments with reference to exemplary embodiment

REFERENCES:
patent: 4112506 (1978-09-01), Zibu
patent: 4554646 (1985-11-01), Yoshimoto et al.
"A 240K Transistor CMOS Array with Flexible Allocation of Memory and Channels", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, Hiromasa Takahashi et al., pp. 1012-1017.
"A 256K CMOS SRAM with Variable Impedance Data-Line Loads", IEEE Journal of Solid-State Circuits, vol. SC-20, No. 5, Oct. 1985, Sho Yamamoto et al., pp. 924-928.

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