CMOS pulse width modulator

Electrical transmission or interconnection systems – Personnel safety or limit control features – Interlock

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Details

307265, 307494, H03K 504, H03K 524

Patent

active

050497618

ABSTRACT:
A pulse width modulator configuration in complementary MOS circuit technology includes two comparators for comparing an input signal with two reference signals and producing results of the comparison. Output stages are associated with the comparators. The output stages are interconnected for logically linking the results of the comparison.

REFERENCES:
patent: 3818249 (1974-06-01), Teranishi et al.
patent: 4238695 (1980-12-01), Hock
patent: 4549151 (1985-10-01), Kaneko
U.S. Publication Electronic Design, vol. 30 (1982), Jul. 8, 1982, No. 14, Waseca, MN, Deuville, N.J., Article "Scaling Down PWM Chip Suits Low-Power Switches", by J. Albernack et al., p. 175, FIG. 1.
U.S. Publication IEEE Journal of Solid State Circuits, vol. SC-17, No. 6, Dec. 1982, New York, Article "MOS Operational Amplifier Design-A Tutorial Overview", by Paul R. Gray et al., pp. 969-981.
German Democratic Republic, Publication Radio, Fernsehen Elektronik, 27th Year, No. 9 (1978-09) Berlin, Article "Schaltungsbeispiele mit CMOS-Schaltkreisen", by G. Turinsky, pp. 551-555, VEB Verlag Technik, Berlin, p. 552, Left Column, Last Paragraph-Right Column, 2nd Paragr., FIG. 5.
U.S. Publication AMK Berlin Congress and Convention Division, ICC Berlin Continuing Engineering Education Program, Seminar 713, Jun. 9-12, 1986, Prel. Edition of "CMOS Analog IC Design and CAD Techniques", by Ph. E. Allen, GA Inst. of Technology, pp. 352-356.

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