CMOS pulse shrinking delay element with deep subnanosecond...

Details CMOS pulse shrinking delay element with deep subnanosecond... CMOS pulse shrinking delay element with deep subnanosecond...

1999-04-07

2001-09-11

Ton, My-Trang Nu (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S286000

Reexamination Certificate

active

06288587

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a CMOS pulse shrinking delay element with deep subnanosecond resolution, and particularly to a CMOS delay element that can control pulse shrinking or expanding merely by changing an aspect ratio or driving capability of adjacent internal elements. A cyclic CMOS Time-to-Digital Converter (TDC) built with the present element has the advantages of extremely fine resolution, low power consumption, and elimination of the need for of bias voltage adjustment or continuous calibrations.
2. Description of the Prior Art
When the IC fabrication process wasn't yet matured, an obsolete subnanosecond order TDC (Time-to-Digital Converter) was usually constructed with high speed ECL components resulting in a relatively large Euro-I printed circuit board with power consumption as high as 5W that was impractical for various portable system applications.
Hence, in order to overcome the abovesaid defects, employment of low power consumption CMOS fabrication process to integrate high density TDC on a substrate seemed to be the inevitable trend. As shown in
FIGS. 1
,
2
, a linear CMOS TDC has been developed since the end of 1995, wherein the pulse shrinking delay element
3
consists of two NOT gates; the first NOT gate contains transistor P
1
and N
1
, the second, P
2
and N
2
respectively. As the maximum conduction current of the first NOT gate is controlled by the gate bias voltage (V
bias
) of transistor N
3
, i.e., the lower the V
bias
the lesser the current in N
3
as well as in the first NOT gate, then accordingly, a V
mid
in flatter slope is formed between those two NOT gates that may shrink the input pulse significantly. In other words, the degree of pulse shrinking in each delay element is controlled by adjusting V
bias
when an input pulse T
in
is propagated through a delay line.
By virtue of the Delay-Locked Loop (DLL) 1, the prior linear CMOS TDC can be continuously calibrated via a V
bias
adjustment to enable an input reference pulse T
ref
to disappear exactly at the last pulse shrinking delay element
3
, which is aggregated to form a delay line
2
a
. Assuming N is the number of total matched delay elements
3
, then the pulse shrinking time in each delay element
3
will be T
ref
/N theoretically.
The continuous calibration will be paused temporarily in the case a time measurement is required, and a pending input pulse T
in
is applied to the input terminal of the TDC for measurement. Assuming the pulse T
in
disappears at the nth element of the delay line
2
a
, the measured width of T
in
would be n×T
ref
/N. For example, in a realized circuit where N equals 64 and pulse width of T
ref
is 50 nanoseconds the resolution of the CMOS TDC is calculated as
50 nanosecond/64=0.78 nanosecond,
which represents the pulse width of the lowest significant bit (LSB).
The abovesaid CMOS TDC circuit can basically meet the requirements of low power consumption, high precision portable TDC systems, however, some defects in need of improvement are listed below:
1. As continuous calibration is required to assure that the reference pulse T
ref
disappear exactly at the last delay element of the delay line
2
a
, logic gates in delay line
2
a
are kept in a toggling state, wasting considerable power.
2. The considerable length and area occupied by delay line
2
a
in a TDC chip may deteriorate the matching of the pulse-shrinking delay elements to badly affect measurement accuracy.
3. A length-doubled delay line
2
a
will be required to merely increase an output bit, and moreover, due to the geometrical confinement of a TDC chip in length and width, an overlong delay line
2
a
has to be folded into segments that may further deteriorate the matching of delay elements. Hence, the maximum number of output bits of a linear CMOS TDC is limited to 6 or 7.
4. As shown in
FIG. 2
, when the pulse width of input T
in
is too narrow, it's possible that V
mid
cannot transit a state below the threshold voltage of the second NOT gate in time and consequently no V
out
output can be obtained. This phenomenon implies that the pulse shrinking time at the last stages (particularly, at the last stage) in a delay line
2
a
is far larger than that in the preceding stages to worsen the TDC measurements accuracy.
In view of the above imperfections, a cyclic CMOS TDC has been proposed since 1997. As shown in
FIG. 3
, the linear delay line
2
a
has been replaced by a cyclic delay line
2
b
that can shrink the input pulse T
in
by a specific width per cycle till T
in
disappears to obtain high resolution of the TDC by proper control of V
bias
.
The improvements made by a cyclic CMOS TDC are:
1. The input pulse T
in
will circulate the delay line
2
b
thoroughly in each cycle to create a constant amount of pulse shrinking per cycle in spite of element mismatch in the delay line
2
b.
2. It is unnecessary for a cyclic CMOS TDC to do what a linear CMOS TDC has to—let a reference pulse T
ref
disappear exactly at the last element (or a designated element) in delay line
2
b
. Hence, the continuous calibration is needless and the cyclic CMOS TDC can be shut down between measurements for power saving.
3. A linear CMOS TDC requires two identical linear delay lines
2
a
with two cooperative DLLs
1
respectively for performing continuous calibration, while a cyclic CMOS TDC only requires one cyclic delay line
2
b
without any DLL
1
that can lower chip size and fabrication cost significantly.
4. The delay line
2
a
must be doubled for a linear CMOS TDC to increase one extra output bit; for a cycling CMOS TDC, it is only necessary to add one more bit to Counter 4 only and properly adjust V
bias
to get enough accuracy without increasing cost.
5. As mentioned above, the width of the input pulse T
in
is shrinks more rapidly in the last stages in the linear delay line
2
a
, which is technically beyond remedy so far. However, it may be deemed as a measurement offset and waived in the cyclic CMOS TDC to highly improve measurement accuracy.
6. For single shot measurement, the cyclic CMOS TDC reveals a stable result with resolution as high as 286 picoseconds and error lower than a half of the resolution (143 psec). Thus, it is unnecessary to average many measurements to improve accuracy. On the contrary, the linear CMOS TDC indicates fluctuated output data with single shot error as large as 3 nanoseconds, and therefore, requires statistical averaging to reduce the measurement error.
To summarize the abovesaid, a cyclic CMOS TDC can indeed eliminate defects derived from the linear CMOS TDC. Nevertheless, a proper external bias voltage is needed to obtain a decent resolution for the cyclic CMOS TDC at the initial calibration. It seems troublesome and lacks of automation, and more importantly, the adjustment of V
bias
for further accuracy improvement of the TDC becomes too trivial and impractical.
Though a subsequent FPGA TDC with resolution of about 200 picoseconds requires no continuous calibration, nor V
bias
adjustment, its single shot error is larger than ½ LSB width and a vital trial-and-error design process is required, and it becomes time-consuming to make the TDC, which is disadvantageous for mass production. The patented inventions in USA relating to Time-to-Digital Converter since 1975 are listed below for reference:
(1) S. Kinbara, et al. “Counting Circuit System for Time-to-digital Converter,” U.S. Pat. No. 4,090,191, May 1978.
(2) J. Genat, et al. “Ultra High-speed Time-to-digital Converter,” U.S. Pat. No. 4,719,608, January 1988.
(3) D. H. Orlov, et al. “Circuit For Measuring Elapsed Time Between Two Events,” U.S. Pat. No. 5,121,012, June 1992.
(4) Rapeli et al. “Method and circuitry for demodulation of angle modulated signals by measuring cycle time,” U.S. Pat. No. 5,270,666. Dec 1993.
In view of the above-described imperfections after years of constant effort in research, the inventors of this invention have consequently developed and proposed this improved mechanism pertaining to the subject

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