CMOS programmable logic array

Details CMOS programmable logic array CMOS programmable logic array

1986-07-23

1987-09-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307469, 307443, 307481, 307594, 307601, 307605, 307246, 364716, H03K 19177, H03K 17284

Patent

active

046971050

ABSTRACT:
A programmable logic array includes a dynamic AND plane, and an OR plane using clocked load devices. The high precharge voltage state in the AND plane places the logic lines in the OR plane in a low voltage state during precharge. The OR logic lines may then be pulled to a high level during the decode operation. A single clock having a delay path may be used to control the precharge and decode operations of the PLA.

REFERENCES:
patent: 4233667 (1980-11-01), Devine et al.
patent: 4488229 (1984-12-01), Harrison
patent: 4501977 (1985-02-01), Koike
patent: 4583012 (1986-04-01), Smith et al.
patent: 4611133 (1986-09-01), Peterson et al.
Leininger, "Universal Logic Module", IBM T.D.B., vol. 13, No. 5, Oct. 1970, pp. 1294-1295.

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