CMOS programmable logic array

Details CMOS programmable logic array CMOS programmable logic array

1984-12-18

1987-03-24

Anagnos, Larry N.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307303, H03K 19094, H03K 19173, H03K 19003

Patent

active

046527770

ABSTRACT:
Large multi-input CMOS logic gates may be formed by a sequence of alternating CMOS NAND and NOR logic gates. The sequence of alternating gates may be compactly laid out in an integrated circuit to form arrays of functional AND or OR gates useful in PLAs. These arrays of CMOS gates consume low power and have response times suitable for integrated circuits.

REFERENCES:
patent: 3943377 (1976-03-01), Suzuki
patent: 3943551 (1976-03-01), Skorup
patent: 4356413 (1982-10-01), Rosenbluth et al.
patent: 4499387 (1985-02-01), Konishi
Bansal, "CMOS(N-Well) Master Image Chip"; IBM-TDB; vol. 26, No. 5, pp. 2404-2406; 10/1983.
Kraft et al, "Method of Personalizing Programmed Logic Arrays Using Multiple Levels of Polysilicon"; IBM-TDB; vol. 23, No. 3, pp. 881-882; 8/1980.

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