CMOS process using doped glass layer

Details CMOS process using doped glass layer CMOS process using doped glass layer

1989-09-25

1991-06-18

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437 44, 437 29, 437 30, 437 27, 437 28, 437 57, 437164, H01L 21225, H01L 21336

Patent

active

050249592

ABSTRACT:
An improved LDD CMOS fabrication is disclosed which uses a reduced number of processing steps. In accordance with one embodiment of the invention, a silicon substrate is provided which has first and second surface regions of opposite conductivity type. First and second silicon gate electrodes overlie the first and second surface regions, respectively. A dopant source layer containing dopant impurities of the first conductivity type is deposited over the first and second gate electrodes. This dopant source layer is patterned to form sidewall spacers at the edges of the first silicon gate electrode. Those sidewall spacers are used in the formation of the LDD structure on the devices formed in the first surface region. After removing the sidewall spacers, the structure is heated to diffuse dopant impurities from the dopant source layer into the second surface region to form source and drain regions of transistors formed in that region. The only lithography step needed in this portion of the process is one to protect the dopant source layer over the second region while sidewall spacers are being formed in the first region.

REFERENCES:
patent: 4488351 (1984-12-01), Momose
patent: 4530150 (1985-07-01), Shirato
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4590663 (1986-05-01), Haken
patent: 4621412 (1986-11-01), Kobayashi et al.
patent: 4642878 (1987-02-01), Maeda
patent: 4714519 (1987-12-01), Pfiester
patent: 4722909 (1988-02-01), Parrillo et al.
patent: 4735916 (1988-04-01), Homma et al.
patent: 4745086 (1988-05-01), Parrillo et al.
patent: 4753898 (1988-06-01), Parrillo et al.
patent: 4757026 (1988-07-01), Woo et al.
patent: 4760033 (1988-07-01), Mueller
patent: 4764477 (1988-08-01), Chang et al.
patent: 4764480 (1988-08-01), Vora
patent: 4784971 (1988-11-01), Chiu et al.
patent: 4818714 (1989-04-01), Haskell
patent: 4822754 (1989-04-01), Lynch et al.
patent: 4826782 (1989-05-01), Sachitano
patent: 4843023 (1989-06-01), Chiu et al.
patent: 4939154 (1990-07-01), Shimbo
patent: 4945070 (1990-07-01), Hsu
Pfiester, "LDD MOSFET's Using Disposable Sidewall Spacer Technology", IEEE Electron Device Letters, vol. 9, No. 4, Apr. 1988, pp. 189-192.

Affiliated with

Also associated with

Rating

CMOS process using doped glass layer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with CMOS process using doped glass layer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and CMOS process using doped glass layer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-145564