CMOS Process for fabricating integrated circuits, particularly d

Details CMOS Process for fabricating integrated circuits, particularly d CMOS Process for fabricating integrated circuits, particularly d

1983-07-14

1985-03-19

Saba, William G.

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 29578, 29579, 29590, 29591, 148174, 156643, 156653, 156657, 1566591, 357 54, 357 59, 427 86, 427 93, H01L 21306, H01L 2131

Patent

active

045050260

ABSTRACT:
A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.

REFERENCES:
patent: 3961999 (1976-06-01), Antipov
patent: 4044454 (1977-08-01), Magdo
patent: 4110125 (1978-08-01), Beyer
patent: 4178674 (1979-12-01), Liu et al.
patent: 4240196 (1980-12-01), Jacobs et al.
patent: 4282648 (1981-08-01), Yu et al.
patent: 4364075 (1982-12-01), Bohr et al.
patent: 4372034 (1983-02-01), Bohr
patent: 4394406 (1983-07-01), Gardiner et al.
patent: 4447290 (1984-05-01), Matthews

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