CMOS process flow with small gate geometry LDO N-channel transis

Details CMOS process flow with small gate geometry LDO N-channel transis CMOS process flow with small gate geometry LDO N-channel transis

1987-04-06

1988-08-16

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 34, 437 44, 437 57, H01L 2702, H01L 2978

Patent

active

047644770

ABSTRACT:
A process for forming lightly doped drains in a CMOS circuit utilizing two photoresist masks is disclosed. After gates for N-channel and P-channel transistors have been formed, an N-implant is effected. A first photoresist mask is used as a source/drain implant is made for the P-channel transistor. Sidewall spacers are formed for the gates of both transistors. A second photoresist mask is used as a source/drain implant is made for the N-channel transistor. The resulting CMOS circuit has an N-channel transistor with a lightly doped drain and a P-channel transistor without a lightly doped drain.

REFERENCES:
patent: 4084311 (1978-04-01), Yasuoka et al.
patent: 4577391 (1986-03-01), Hsia et al.
patent: 4590663 (1986-05-01), Haken
patent: 4717684 (1988-01-01), Katto et al.
Lee et al., IEDM Tech. Digest, Electron Devices Meeting, Washington, D.C. (Dec.1985), pp. 242-245.

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