CMOS process compatible self-alignment lateral bipolar junction

Details CMOS process compatible self-alignment lateral bipolar junction CMOS process compatible self-alignment lateral bipolar junction

1995-06-07

1997-09-23

Prenty, Mark V.

Active solid-state devices (e.g., transistors, solid-state diode

Bipolar transistor structure

257575, 257592, 257593, H01L 27082

Patent

active

056708220

ABSTRACT:
A self aligned lateral BJT is disclosed which has a lightly doped first region of a first conductivity type, e.g., P-type. A heavily doped poly region, of a second conductivity type, e.g., N-type, is provided on a portion of a surface of the first region. A heavily doped second region of the second conductivity type, is disposed in the first region below the poly region. An oxide region is provided on a portion of the first region surface adjacent to the poly region. A third region of the first conductivity type is disposed in the first region adjacent to the second region and below the oxide region. A heavily doped fourth region of the second conductivity type is disposed in the first region adjacent to the third region. The fabrication of the lateral BJT includes the step of forming a poly region on a portion of the first region. Then, the second region is formed by diffusing an impurity from the poly region into the first region. The third region is then formed adjacent to the second region. A portion of a surface of the third region near the second region is covered with the oxide region. Thereafter, the fourth region is formed adjacent to the third region by implanting ions into an uncovered surface portion of the third region.

REFERENCES:
patent: 4329703 (1982-05-01), Priel et al.
patent: 5323057 (1994-06-01), Cook et al.
IBM Technical Disclosure Bulletin, vol. 22, #7, pp. 2939-2942 Dec. 1979 by Feth et al.
S.A. Abbas and I.E. Magdo, Lateral PNP, IBM Tech. Disc. Bul., vol. 25, No. 11A, Apr. 10, 1983, pp. 5727-5728.

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