CMOS process and circuit including zero threshold transistors

Details CMOS process and circuit including zero threshold transistors CMOS process and circuit including zero threshold transistors

1994-12-02

1996-02-20

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific identifiable device, circuit, or system

Integrated structure

327581, 437 45, H01L 2500

Patent

active

054932513

ABSTRACT:
A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FET' channels in addition to the implantation required to raise the PMOS FET' threshold voltage from the native threshold voltage to the normal threshold voltage.

REFERENCES:
patent: 4103189 (1978-07-01), Perlegos et al.

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