CMOS process and circuit including zero threshold transistors

Details CMOS process and circuit including zero threshold transistors CMOS process and circuit including zero threshold transistors

1992-06-23

1995-04-18

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 30, 437 57, 148DIG70, H01L 21266

Patent

active

054078490

ABSTRACT:
A method of threshold adjust implantation which involves the implanting of some of the PMOS FETs' channels on a CMOS circuit so the PMOS FETs have a threshold voltage of substantially zero volts, the implanting involves an additional implantation of ions into the PMOS FETs' channels in addition to the implantation required to raise the PMOS FETs' threshold voltage from the native threshold voltage to the normal threshold voltage.

REFERENCES:
patent: 4422885 (1983-12-01), Brower et al.
patent: 4845047 (1989-07-01), Holloway et al.
patent: 5091324 (1992-02-01), Hsu et al.
patent: 5270235 (1993-12-01), Ito

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